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ds97key2005 p r e l i m i n a r y 1 p reliminary p roduct s pecification z8e520/c520 1 1.5 mbps usb l ow -p ower d evice c ontroller f or m ultiprotocol p ointing d evices features n six vectored interrupts with fixed priority n processor speed dividable by firmware control n operating current: 5 ma typical in usb mode; 2.5 ma typical in serial mode (@ 3 mhz); 5 ma typical in ps/2 mode n 16 total input/output pins (open-drain/push-pull) configurable n 6 inputs with 3 level programmable reference comparators n 16-bit programmable watch-dog timer (wdt) with internal rc oscillator n software programmable timers configurable as: two 8-bit standard timers and one 16-bit standard timer or one 16-bit standard timer and one 16-bit pulse width modulator (pwm) timer n identical masked rom version (z8c520) n on-chip oscillator that accepts a ceramic resonator or external clock n hardware support for ps/2, serial, usb, and general- purpose i/o (gpio) n power reduction modes: stop mode (functionality shut down except smr) halt mode (xtal still running-peripherals active) n usb sie compliant with usb spec 1.0 n 4.0 vdc to 6.0 vdc operating range @ 0 c to +70 c general description zilog? z8e520 (otp) and z8c520 (masked rom) micro- controllers are low-power z8 plus mcus, designed for the cost-effective implementation of usb and multiprotocol pointing devices. for applications demanding powerful i/o capabilities, the z8e520's input and output lines are grouped into two ports, and are configurable under software control to provide tim- ing, status signals, or parallel i/o. both 8-bit and 16-bit timers, with a large number of user se- lectable modes, off-load the system of administering real- time tasks such as counting/timing and i/o data communi- cations. the microcontroller clock frequency is derived from the system clock by a programmable divider under firmware control. the device is capable of functioning in four distinct, select- able communications modes: ps/2, rs232, gpio (gener- al-purpose i/o), and usb. the communications mode de- termines the functionality of the two special serial communications pins (pb6 and pb7). the device is placed in the required mode when firmware sets the specified mode bit in the communications control register. the firm- ware interface is similar in all modes. the same buffer area in ram will accept the data to be transmitted. up to 8 bytes may be loaded, and the data will actually be transmitted as soon as the appropriate command is issued (setting in packet ready in usb mode, for example). part rom ram speed number (kb) (bytes) (mhz) z8e520 (otp) 6 176 12 z8c520 (rom) 6 176 12
z8e520/c520 1.5 mbps usb device controller zilog 2 p r e l i m i n a r y ds97key2005 general description (continued) power connections follow conventional descriptions at right: connection cir cuit de vice p o w er v cc v dd ground gnd v ss figure 1. z8e520 functional bloc k dia gram one 16-bit std. timer interr upt control 6 analog compar ators alu flag register p ointer ram register file (160 bytes) machine timing & inst. control 6 k bytes prg. memor y prog r am counter v cc gnd ceramic resonator port a port b i/o two 8-bit timers or one 16-bit pwm timer i/o zie wdt rc osc internal p or t b (6?)
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 3 1 communication modes the z8e520/c520 allows its user to function in a variety of communication modes. having this freedom within a sin- gle chip opens up many possibilities when utilizing multiple protocol applications. the modes incorporated into the z8e520/c520 include ps/2, rs232, gpio, and usb. a description of each mode is detailed below. ps/2 mode . the serial baud rate is fixed at 12.5 k baud. received data is automatically checked for parity and framing errors while host abort is supported. the serial communications pins function as ps/2 compatible data (pb6) and clock (pb7). rs232 mode. the data rate is fixed at 1200 baud . the se- rial communications pins function as rxd (pb6) and txd (pb7). gpio mode . in general-purpose i/o mode, the serial communications pins function as standard i/o pins, with input, output p/p (push/pull) and od (open drain) out- put. usb mode . the z8e520 includes two bidirectional end- points that support communications compliant to the usb specification version 1.0. the serial communications pins function as d?(pb6) and d+ (pb7). the detailed behavior of the sie is controllable by the firmware, and three sepa- rate power states are provided for usb suspend mode support (see section below). usb suspend/resume functionality suspend is dedicated through firmware by timing the ac- tivity bit which is set by the sie. in stop mode, with the wdt disabled, power requirements are minimized. no power is consumed by the voltage reg- ulator, the z8 plus core, nor differential detector. only the stop mode recovery (smr) is enabled, so an input signal or resume from the host can be detected and used to wake up the microcontroller. in stop mode, with the wdt enabled, slightly more power is consumed, but the device can wake up periodically to perform maintenance and detect a change of state in the application. usb functional block description the usb portion of the chip is divided into two areas, the transceiver and the serial interface engine (sie). the transceiver handles incoming differential signals and ?in- gle ended zero (se0)? it also converts output data in digi- tal form to differential drive at the proper levels (figure 2). the sie performs all other processing on incoming and out going data, including signal recovery timing, bit stuffing, validity checking, data sequencing, and handshaking to the host. data flow into and out of the mcu portions are dedicated registers mapped into expanded register file memory. the usb sie handles three endpoints (control at endpoint 0, data into the host from endpoint 1 and data out from the host as endpoint 2). all communications are at the 1.5 mb/sec data rate. endpoint 1 and 2 can be combined as control ep1. figure 2. data t o/fr om z8e520/c520
z8e520/c520 1.5 mbps usb device controller zilog 4 p r e l i m i n a r y ds97key2005 pin identification figure 3. 20-pin dip/soic pin assignments p a6 p a7 pb0 pb1 pb2 pb3 pb4 pb5 p a0 p a1 p a5 p a4 xt al (2) gnd xt al (1) vcc pb7 pb6 p a3 p a2 20 20-pin dip/soic 1 10 11 t ab le 1. 20-pin dip/soic pin identi cation st and ard mode pin # symbol function direction 1, 2 p a x( 6,7) digital i/o + i sink bidirectional 3? pb x(0?) digital i/o +compar ators bidirectional 9?2 p a x(0?) digital i/o bidirectional 13?4 pb x (6?) digital i/o + comm unications bidirectional 15 v cc p o w er 16 xt al (1) cloc k 17 gnd p o w er 18 xt al (2) cloc k 19, 20 p a x( 4,5) digital i/o + i sink bidirectional
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 5 1 figure 4. 20-pin dip/soic pin assignments: epr om pr ogramming mode d0 d1 d2 d3 d4 d5 d6 d7 tst_clr pgm clk (1 mhz) gnd (clk out) vcc vpp addrclk 20 20-pin dip/soic 1 10 11 t ab le 2. 20-pin dip/soic pin identi cation: epr om pr ogramming mode epr om pr ogramming mode pin # symbol function direction 1? d0?7 data bus i/o 9 tst_clr reset inter nal address counter in 10 pgm p rog r am pin in 11 addrclk cloc k to address counter in 12 v pp high v oltage to prog r am de vice p o w er 13?4 un used 15 v cc p o w er p o w er 16 clk out output from cloc k in v er ter out 17 gnd p o w er ref p o w er 18 clk 1 mhz to chip in 19 un used 20 un used
z8e520/c520 1.5 mbps usb device controller zilog 6 p r e l i m i n a r y ds97key2005 absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this rating is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. total power dissipation should not exceed 880 mw for the package. power dissipation is calculated as follows: t otal p o w er dissipation = v dd x [i dd ?(sum of i oh )] + sum of [(v dd ? v oh ) x i oh ] + sum of (v 0l x i 0l ) p arameter min max units note ambient t emper ature under bias ?0 +105 c stor age t emper ature ?5 +150 c v oltage on an y pin with respect to v ss ?.6 +7 v v oltage on v dd pin with respect to v ss ?.3 +7 v t otal p o w er dissipation 880 mw maxim um allo w ab le current out of v ss 80 ma maxim um allo w ab le current into v dd 80 ma maxim um allo w ab le current into an input pin ?00 +600 m a 1 maxim um allo w ab le current into an open-dr ain pin ?00 +600 m a 2 maxim um allo w ab le sink output current b y an y i/o pin 25 ma maxim um allo w ab le source output current b y an y i/o pin 25 ma maxim um allo w ab le sink output current b y p or t a 40 ma maxim um allo w ab le source output current b y p or t a 40 ma maxim um allo w ab le sink output current b y p or t b 40 ma maxim um allo w ab le source output current b y p or t b 40 ma notes: 1. excludes xtal pins. 2. device pin is not at an output low state.
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 7 1 standard test conditions the characteristics listed here apply for standard test con- ditions as noted. all voltages are referenced to gnd. pos- itive current flows into the referenced pin (figure 5). capacitance t a = 25 c; v cc = gnd = 0v; f = 1.0 mhz; unmeasured pins returned to gnd. figure 5. test load diagram from output under test 150 pf p arameter max input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf note: frequency tolerance 10%
z8e520/c520 1.5 mbps usb device controller zilog 8 p r e l i m i n a r y ds97key2005 dc characteristics: usb mode v cc = 4.4v ?5.25v t a = 0 c to +70 c sym p arameter v cc min max units conditions notes v ch cloc k input high v oltage 0.7v cc v cc +0.3 v dr iv en b y exter nal cloc k gener ator v cl cloc k input lo w v oltage v ss ?.3 0.2v cc v dr iv en b y exter nal cloc k gener ator v ih input high v oltage 0.7v cc v cc +0.3 v v il input lo w v oltage v ss ?.3 0.2v cc v v oh output high v oltage (p or t a, b) v cc ?.4 v i oh = ?.0 ma v ol1 output lo w v oltage (p or t a, b) 0.6 v i ol = +4.0 ma 4 v ol2 output lo w v oltage (p or t a, b) 1.2 v i ol = +6 ma, 4 v offset compar ator input offset v oltage 25.0 mv i il input leakage ?.0 2.0 m a v in = 0v , v cc i ol output leakage ?.0 2.0 m a v in = 0v , v cc v icr compar ator input common mode v oltage range v ss ?.3 v cc ?.0 v i cc supply current 6.0v 5.25 6.0 ma @ 6 mhz (inter nal open dr ain) 1,2 i cc1 hal t mode 6.0v 3.5 ma @ 6 mhz (no cpu; rc/wdt & detect; d+/d? i/o activ e) 1,2 i cc2 stop current 60 m a i cc3 stop current w/o rc/wdt 40 m a d+, d diff erential signaling d?> d+ d+ > d mv @ >200 mv diff erence 3 notes: 1. all outputs unloaded, i/o pins floating, and all inputs are at v cc or v ss level. 2. cl1 = cl2 = 22 pf 3. except for se0 for eop and reset (see 7.1.4 of usb specification) 4. general-purpose i/o mode.
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 9 1 dc characteristics: ps/2 mode v cc = 4.5v ?5.5v t a = 0 c to +70 c sym p arameter v cc min max units conditions notes v ch cloc k input high v oltage 0.7v cc v cc +0.3 v dr iv en b y exter nal cloc k gener ator v cl cloc k input lo w v oltage v ss ?.3 0.2v cc v dr iv en b y exter nal cloc k gener ator v ih input high v oltage 0.7v cc v cc +0.3 v v il input lo w v oltage v ss ?.3 0.2v cc v v oh output high v oltage v cc ?.4 v i oh = ?.0 ma v ol1 output lo w v oltage 0.6 v i ol = +4.0 ma v ol2 output lo w v oltage 1.2 v i ol = +6 ma, v offset compar ator input offset v oltage 25.0 mv i il input leakage ?.0 2.0 m a v in = 0v , v cc i ol output leakage ?.0 2.0 m a v in = 0v , v cc v icr compar ator input common mode v oltage range v ss ?.3 v cc ?.0 v i cc supply current 5.5v 6.0 ma @ 6 mhz 1,2 i cc1 hal t current 5.5v 3.5 ma @ 6 mhz (no cpu; no sie) 1,2 i cc2 stop current 60 m a i cc3 stop current w/o rc/wdt 40 m a notes: 1. all outputs unloaded, i/o pins floating, and all inputs are at v cc or v ss level. 2. cl1 = cl2 = 22 pf.
z8e520/c520 1.5 mbps usb device controller zilog 10 p r e l i m i n a r y ds97key2005 dc characteristics: rs232 mode v cc = 4.0v ?6.0v t a = 0 c to +70 c sym p arameter v cc min max units conditions notes v ch cloc k input high v oltage 0.7v cc v cc +0.3 v dr iv en b y exter nal cloc k gener ator v cl cloc k input lo w v oltage v ss ?.3 0.2v cc v dr iv en b y exter nal cloc k gener ator v ih input high v oltage 0.7v cc v cc +0.3 v v il input lo w v oltage v ss ?.3 0.2v cc v v oh output high v oltage v cc ?.4 v i oh = ?.0 ma v ol1 output lo w v oltage 0.6 v i ol = +4.0 ma v ol2 output lo w v oltage 1.2 v i ol = +6 ma, v offset compar ator input offset v oltage 25.0 mv i il input leakage ?.0 2.0 m a v in = 0v , v cc i ol output leakage ?.0 2.0 m a v in = 0v , v cc v icr compar ator input common mode v oltage range v ss ?.3 v cc ?.0 v i cc supply current 6.0v 4.0 ma @ 3 mhz (6 mhz/2) 1,2 i cc1 hal t mode 6.0v 3.5 ma @ 3 mhz 1,2 i cc2 stop current 60 m a i cc3 stop current w/o rc/wdt 40 m a notes: 1. all outputs unloaded, i/o pins floating, and all inputs are at v cc or v ss level. 2. cl1 = cl2 = 22 pf.
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 11 1 dc characteristics: i/o mode v cc = 4.0v ?6.0v t a = 0 c to +70 c sym p arameter v cc min max units conditions notes v ch cloc k input high v oltage 0.7v cc v cc +0.3 v dr iv en b y exter nal cloc k gener ator v cl cloc k input lo w v oltage v ss ?.3 0.2v cc v dr iv en b y exter nal cloc k gener ator v ih input high v oltage 0.7v cc v cc +0.3 v v il input lo w v oltage v ss ?.3 0.2v cc v v oh output high v oltage v cc ?.4 v i oh = ?.0 ma v ol1 output lo w v oltage 0.6 v i ol = +4.0 ma v ol2 output lo w v oltage 1.2 v i ol = +6 ma, v offset compar ator input offset v oltage 25.0 mv i il input leakage ?.0 2.0 m a v in = 0v , v cc i ol output leakage ?.0 2.0 m a v in = 0v , v cc v icr compar ator input common mode v oltage range v ss ?.3 v cc ?.0 v i cc supply current 6.0v 6.0 ma @ 6 mhz 1,2 i cca 5.5v 6.0 ma @ 5.5v 1,2 i ccb 4.0 ma @ 6.0v (6 mhz/2) i cc1 hal t w/ rc and wdt 60 m a i cc2 50 m a notes: 1. all outputs unloaded, i/o pins floating, and all inputs are at v cc or v ss level. 2. cl1 = cl2 = 22 pf.
z8e520/c520 1.5 mbps usb device controller zilog 12 p r e l i m i n a r y ds97key2005 ac electrical characteristics timing diagram timing table figure 6. a c electrical timing dia gram 1 3 3 2 2 clock irq n 8 9 t a = 0 c to +70 c 6 mhz no symbol p arameter min max units notes 1 tpc input cloc k p er iod 83 dc ns 1 2 t rc ,tfc cloc k input rise & f all times 5 ns 1 3 t wc input cloc k width 37 ns 1 4 t wtinl timer input lo w width 70 ns 1 5 t wtinh timer input high width 2.5tpc 1 6 tptin timer input p er iod 4tpc 1 7 t rtin timer input rise & f all timer 100 ns 1 8 t wil int. request lo w time 70 ns 1,2 9 t wih int. request input high time 3tpc 1,2 10 t wsm stop-mode reco v er y width spec 100tpc ns 11 t ost oscillator star t-up time 0.5 ms 12 t wdt w atch-dog timer 1000 ms 13 d+, d diff erential rise and f all times (usb mode) 70 300 ns 3 14 por p o w er supply; por r ate/v olt le v el 15 t rc rc cloc k p er iod (inter nal) 12.5 50 m sec 4 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request 3. see usb specification 7.1.1.2 4. corresponds to frequencies of 80 khz to 20 khz
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 13 1 pin functions port a . port a (4?) includes a sink configuration. port a (3?) has a switch configuration. in sink, the options include input wakeup, bidirectional, push-pull or open drain configurations (figure 7). the sink is programmable from 0?5 ma (in 1 ma increments). in switch, the options also include input wakeup, bidirec- tional, push-pull or open drain configurations (figure 8). the only difference between the two is the programmable sink option. figure 7. p or t a (4?) sink con guration t ab le 3. port a (4?) programmable current sink table symbol parameter min. max. units conditions n number of bits bits 4 bits, 16 settings, 0?5 ma dnl diff non-linearity 0.50 lsb i 0 zero code/disable m a disabled i lsb lsb current 0.65 1.35 ma 35% i f full scale current 9.75 20.25 ma 35% , note 1 t settle settling time 1600 ns within 10% of final value i overshoot overshoot current 1.05*i set m a v comp compliance voltage 1.1 v above v ss with i fmax notes: 1. s etting all (4) i snk cells to full scale is a violation of the absolute maximum rating spec. 0 1 5 m a / 1 m a i n c r e m e n t s p a d 1 0 0 k i n v c c v c c w a k e t b d 3 0 % i s i n k ( 3 : 0 ) pullup resistor enable typical
z8e520/c520 1.5 mbps usb device controller zilog 14 p r e l i m i n a r y ds97key2005 pin functions (continued) figure 8. p or t a (0?) switc h con guration p a d 1 0 0 k p u l l - d o w n resistor enable i n w a k e v c c ( 35%)
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 15 1 port b . port b (0?) includes a quadrature configuration (figure 9), with programmable current sink and an analog comparator with programmable reference voltages (ta- bles 4 8) . port b (0?) quadrature configuration figure 9. p or t b (0?) quadrature con guration t ab le 4. programmable voltage threshold symbol p arameter min. max. units conditions v r1 v oltage ref erence 1 0.21 v cc 0.29 v cc v v r2 v oltage ref erence 2 0.31 v cc 0.39 v cc v v r3 v oltage ref erence 3 0.41 v cc 0.49 v cc v ratio ratio accur acy 5 % note (1) note: 1. greatest delta vs. specified delta. p a d a c a c d ecode v r1 v r3 v r2 + v + v ac = analog comparator mode
z8e520/c520 1.5 mbps usb device controller zilog 16 p r e l i m i n a r y ds97key2005 port b (0?) quadrature configuration (continued) t ab le 5. programmable voltage bit selections (register addresses da df) comp enab le bit d7 v ref bits d5:4 selected conditions 0 x x compar ator off note (1) 1 0 1 0.25 v cc 1 10 0.35 v cc 1 1 1 0.45 v cc note: 1. if all comparators are off, v ref can be powered off. if in stop mode, v ref is powered off. t ab le 6. programmable load resistor symbol p arameter min. max. units conditions v mid midpoint v oltage 0.13 v cc 0.15 v cc v r l1 load resistor 1 5.25 8.75 k ohm p ad to v ss , tr ac k r l2 , r l3 r l2 load resistor 2 9.00 15.00 k ohm p ad to v ss , tr ac k r l1 , r l3 r l3 load resistor 3 13.50 22.50 k ohm p ad to v ss , tr ac k r l1 , r l2 r l4 load resistor 4 32.25 53.75 k ohm p ad to v cc r l5 load resistor 5 55.50 92.50 k ohm p ad to v cc r l6 load resistor 6 83.25 138.75 k ohm p ad to v cc ratio ratio accur acy 5 % note (1) note: 1. greatest ratio vs. specified ratio. t ab le 7. programmable load resistor bit selections (register addresses da df divider bits d 2 :0 load selected to v ss load selected to v cc 00 0 no load resistors no load resistors 00 1 7 k selected 43 k selected 01 0 12 k selected 74 k selected 100 18 k selected 111 k selected t ab le 8. comparator symbol p arameter min. max. units conditions v os offset v oltage 25 mv hys hysteresis tbd tbd mv common mode , note (1) vcm v oltage range v ss ?.3 v cc ?.0 v t rf response time f ast 1 m s 700 mv/ m s with 25 mv o v erdr iv e t rs response time slo w 1 m s 15 mv/ m s with 25 mv o v erdr iv e idd supply current 100 m a note: 1. zilog will provide specification.
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 17 1 port b. port b (6?) is configured as a serial communica- tion port as follows: port b (6) has a programmable internal pullup of 7.5 k 30%. for usb mode, port b (7) requires an external pullup of 7.5 k 1% to v cc (figure 10). usb ps/2 rs232 gpio p or t b (6) d data r x d p or t b (6) p or t b (7) d + cloc k t x d p or t b (7) figure 10. p or t b (6?) serial comm unication p or t p a d p u l l - up resistor enable i n / w a k e v u s b 7 . 5 k p u l l u p v c c v c c
z8e520/c520 1.5 mbps usb device controller zilog 18 p r e l i m i n a r y ds97key2005 functional description program memory. the 16-bit program counter addresses 6 kb of program memory space at internal locations (figure 11). the first 14 bytes of program memory are reserved for the rollover and interrupt vectors. these locations have six 16- bit vectors that correspond to the six available inter- rupts. figure 11. z8e520 pr ogram memor y map irq0 irq1 irq2 irq3 irq4 irq5 hex 17ff 00d 00c 00b 00a 009 008 007 006 005 004 003 002 001 000 00e 01f 020 021 location of first byte of instruction executed after reset available to user (area intended for future additional interrupts) on-chip eprom program memory decimal address 6143 33 32 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 irq0 irq1 irq2 irq3 irq4 irq5 pc rollover vector (upper byte) pc rollover vector (lower byte) interrupt vector (lower byte) interrupt vector (upper byte)
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 19 1 register file . the register file consists of the following: 160 general-purpose registers in group 0?, sie buffers in group 8?, sie control in group b, timer/counters in group c, configuration registers in group d, virtual reg- isters in group e and system registers in group f (figure 12). figure 12. register files t ab le 9. ep modes for sie buffer (in usb mode) ep mode description buff er ad dress 0x88?x8f 0x98?x9f 0xa8?xaf 000 ep1 off , ep2 off gpr gpr gpr 001 ep1 in, ep2 off gpr gpr epi in buff er 010 ep1 out , ep2 off gpr gpr ep1 out buff er 011 ep1 contr ol ep1 setup buff er ep1 out buff er ep1 in buff er 100 ep1 out , ep2 out gpr ep2 out buff er ep1 out buff er 101 ep1 in, ep 1 o ut gpr ep 1 o ut buff er ep1 in buff er 110 ep1 out , ep 1 i n gpr ep 1 i n buff er ep1 out buff er 111 ep1 in, ep2 in gpr ep2 in buff er ep1 in buff er 0 1 4 2 3 5 6 7 8 9 a b c d e f general-purpose registers system registers v irtual registers i/o configuration t imer/counter sie control ep0 out buffer ep0 in buffer ep0 setup buffer xmit buffer receive buffer general purpose ram a 9 8 depends on ep mode (see t able below) sie buffers (for ps/2 or rs232-c mode) sie buffers (for usb mode)
z8e520/c520 1.5 mbps usb device controller zilog 20 p r e l i m i n a r y ds97key2005 functional description (continued) figure 13. system register s f0 f1 f4 f2 f3 f5 f6 f7 f8 f9 f a fb fc fd fe ff ireq imask flags regptr reser ved st ack pointer reserved
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 21 1 figure 14. t/c contr ol register s c0 c1 c4 c2 c3 c5 c6 c7 c8 c9 ca cb cc cd ce cf tctllo tctlhi wdtlo wdthi t0arlo t1arlo t0arhi t1arhi t2ar t3ar t2c nt t3c nt t0cnt t1cnt reser ved reser ved read only
z8e520/c520 1.5 mbps usb device controller zilog 22 p r e l i m i n a r y ds97key2005 functional description (continued) figure 15. comm register s (usb mode: b0?f) addr b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf name d7 d6 d5 d4 d3 d2 d1 d0 port a port b addr sie mode usb csr low priority intr low priority mask high priority intr high priority mask ep0 csr usb address 6:0 sie power resume force resume nak sent ep1 activity nak sent ep0 sie mode 7:0 st all sent ep2 a7 a6 a5 a4 a3 a2 a1 a0 b5 b4 b3 b2 b1 b0 ep mode 2:0 depends on ep mode (see t able 10) depends on ep mode (see t able 10) st all sent ep1 st all sent ep0 setup ep1 setup ep0 same as high proiority intr ack st a tus out setup buffer vola tile out ser viced out da t a t oggle force st all force nak in p acket ready in da t a t oggle ep1/2 csr depends on ep mode (see t able 11) ep0 count ep0 out count 3:0 ep0 in count 3:0 ep1/2 count depends on ep mode (see t able 12) rs232 ps/2 usb j state b7 b6
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 23 1 communication register definitions (usb mode) the following definitions on pages 23?6 describe in detail the specific usb mode registers as illustrated in figure 15. port a, port b : i/o port data registers. at all times, a read to this port should indicate the current state at the pins. read/write. addr : determines the usb device address. cleared by usb or por reset. read/write. sie mode : determines the mode of the sie communica- tion pins (port b7:6). read/write. the sie modes are as follows: gpio : the sie is off and the communication lines are standard i/o pins on port b. usb : port b7 is d+, which connects to pin 3 on a series a, or series b usb connector and whose conductor is green. port b6 is d? which connects to pin 2 on a series a or se- ries b usb connector and whose conductor is white. an external 7.5k pull-up should be provided for d? ps/2 : port b7 is clock, which connects to pin 5 on a male 6-pin mini-din connector and port b6 is data, which connects to pin 1 on a male 6-pin mini-din connector. these signals are open-drain. the clock pin has an available 7.5 k ohm pull-up internal to the chip. an external 7.5 k ohm pull-up should be provided for data. rs232 : port b7 is serial data out (t x d) . port b6 is serial data in (r x d) . these signals are cmos-level signals, positive logic. appropriate transceiver circuitry must be added externally to comply with rs232-c signal levels at the device connector. sie power : powers up the sie when usb resume sig- naling has been received, or shuts down sie in prepara- tion for usb suspend. read/write. force resume : forces a k state on the usb pins. read/write. activity : this bit is set by the sie when the state of the usb pins changes. read/write. j state : this bit is set when the usb is in the ??state and cleared when in ??or ?e0? read only. ep mode : these bits define the operation of the non-zero endpoints of the sie. changing this mode resets the sie, while writing the same value does not. read/write. the ep modes are as follows: sie mode description p or t b7 p or t b6 00000000 gpio i/o i/o 00000001 usb d+ d 00000010 ps/2 clock d a t a 00000100 rs232-c 1200 baud n81 full duple x d a t a in d a t a out other reser v ed reser v ed reser v ed ep mode description 000 ep1 off , ep2 off 001 ep1 in, ep2 off 010 ep1 out , ep2 off 011 ep1 contr ol 100 ep1 out , ep2 out 101 ep1 in, ep 1 o ut 110 ep1 out , ep 1 i n 111 ep1 in ep2 in
z8e520/c520 1.5 mbps usb device controller zilog 24 p r e l i m i n a r y ds97key2005 communication register definitions (usb mode) (continued) low priority intr : this register contains the irq source flags of a low-priority communications interrupt. the isr should check these bits to determine the cause of the interrupt. the definition of these bits depends on the ep mode as specified in the usb csr. writing a 1 to their position clears interrupt sources. read/write. low priority mask : this register contains mask bits for the irq sources specified in the low priority intr register. a set bit indicates that the corresponding interrupt source is unmasked. table 10 illustrates both low priority mask and intr con- ditions according to ep mode: in done : the sie received a valid in token, sent the data packet and received an ack from the host. setting this bit by the sie, clears in packet ready and in nak sent. sie may never write to the in buffer. in nak sent : the sie sent a nak on an in transmission because in packet ready was clear. out packet ready: the sie received a valid out packet and placed the received data, if any, in the buffer, thereby updating the out count register and sending an ack. setting this bit by the sie clears out serviced and out nak sent. firmware may never write to the out buffer. out nak sent : the sie sent a nak on an out trans- action because out serviced was clear. if an out packet was nak?, out data toggle and the out buffer must not be affected. t ab le 10. lo w priority mask and intr conditions ep mode description ep 2 ep 1 ep 0 000 ep1 off , ep2 off out nak sent out p a cket read y in nak sent in done 001 ep1 in ep2 off in nak sent in done out nak sent out p a cket read y in nak sent in done 010 ep1 out , ep2 off out nak read y out p a cket read y out nak sent out p a cket read y in nak sent in done 011 ep1 contr ol out nak sent out p a cket read y in nak sent in done out nak sent out p a cket read y in nak sent in done 100 ep1 out , ep2 out out nak sent out p a cket read y out nak sent out p a cket read y out nak sent out p a cket read y in nak sent in done 101 ep1 in, ep1 out out nak sent out p a cket read y in nak sent in done out na ck sent out p a cket read y in nak sent in done 110 ep1 out , ep1 in in nak sent in done out nak sent out p a cket read y out nak sent out p a cket read y in nak sent in done 111 ep1 in ep2 in in nak sent in done in nak sent in done out na ck sent out p a cket read y in nak sent in done
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 25 1 high priority intr : this register contains the irq source flags of a high-priority communications interrupt. the isr should check these bits to determine the cause of the interrupt. writing a 1 to their position clears interrupt sources. read/write. n resume : this bit is set when the activity bit is set in the usb csr, allowing the device to wake up on any activity of the usb. n stall sent ep2 : this bit is set when a stall is sent on ep2. this bit is valid only in ep modes 100, 101, 110 and 111. n stall sent ep1 : this bit is set when a stall is sent on ep1. this bit is not valid in ep mode 000. n stall sent ep0 : this bit is set when a stall is sent on ep0. n setup ep1 : this bit is set after the completion of the setup stage of a control transfer on ep1. this bit is valid only in ep mode 011. n setup ep0 : this bit is set after the completion of the setup stage of a control transfer on ep0. high priority mask : this register contains mask bits for the irq sources specified in the high priority intr register. a set bit indicates that the corresponding interrupt source is unmasked. ep0 csr : control/status register of endpoint 0 (control pipe). ep1/2 csr : control/status register of additional end- points. the definition of these bits depends on the ep mode as specified in the usb csr. read/write. table 11 illustrates the ep1/2 csr registers according to ep mode: force stall : forces the sie to stall all in and out transactions. the successful receipt of a setup token clears this bit. stall takes priority over nak or ack. read/write. in packet ready : when clear, in transactions are nak?. this bit cannot be cleared by firmware. to clear it, firmware should be set force nak. firmware must not write to the in buffer or in count while this bit is set. it is cleared when the sie sets in done or when the sie re- t ab le 11. ep 1/2 csr register s (b a) ep mode description ep 1 000 ep1 off , ep2 off force st all force nak in p a cket read y in d a t a t oggle 001 ep1 in ep2 off force st all force nak in p a cket read y in d a t a t oggle 010 ep1 out , ep2 off force st all force nak out p a cket read y out d a t a t oggle 011 ep1 contr ol a ck st a tus out setup b uffer v ola tile out ser viced out d a t a t oggle force st all force nak in p a cket read y in d a t a t oggle 100 ep1 out , ep2 out force st all force nak out ser viced out d a t a t oggle force st all force nak out p a cket read y out d a t a t oggle 101 ep1 in, ep1 out force st all force nak out ser viced out d a t a t oggle force st all force nak in p a cket read y in d a t a t oggle 110 ep1 out , ep1 in force st all force nak in p a cket read y in d a t a t oggle force st all force nak out p a cket read y out d a t a t oggle 111 ep1 in ep2 in force st all force nak in p a cket read y in d a t a t oggle force st all force nak in p a cket read y in d a t a t oggle
z8e520/c520 1.5 mbps usb device controller zilog 26 p r e l i m i n a r y ds97key2005 communication register definitions (usb mode) (continued) ceives a valid setup token (via force nak). setting in packet ready clears in nak sent. read/set. force nak : setting this bit clears in packet ready if no in transaction are in progress, and clears out ser- viced and ack status out if no out transactions are in progress. this bit is cleared by a setup token or by firm- ware. read/write. in data toggle : indicates what type of pid to use in the data phase of the next in transaction. sie may never write to this bit. read/write. out serviced : when cleared, out transactions are nak?. it is cleared when the sie sets out packet ready or receives a valid setup token (via force nak). this bit cannot be cleared by firmware. to clear it, firm- ware should be set force nak. when set, out count and out buffer are volatile. setting out serviced clears out n ak sent. read/set. out data toggle : indicates what type of pid was re- ceived in the data phase of the most recent successful out transaction. read only. setup buffer volatile : indicates that the sie has entered the data stage of a control transfer. the successful receipt of a setup token sets and locks this bit. the bit re- mains locked as set until the data phase is complete and error free. if the data phase has an error, this bit will re- mained locked, but a setup interrupt will still occur to inform the firmware that a new transfer was attempted. after the data phase is received without errors, firmware may clear this bit. read/clear (if unlocked). ack status out : this bit serves to filter the response to an out transaction. setting this bit also sets out ser- viced. this bit cannot be cleared by firmware. to clear it, firmware should be set force nak. read/set. while ack status out is set: n if in nak sent is clear, the sie will ack an empty out data 1 transaction. n if in nak sent is set, the sie will nak an empty out data 1 transaction. n any other kind of out transaction will be stalled and set the stall sent interrupt. it is possible to have both stall sent and out packet ready set on a single, incorrect out transaction. n any out transaction will cause the sie to set force nak and out packet ready. as a result, ack status out is cleared. ack status out has ?ne- shot?behavior. it only handles one out transaction. n the successful receipt of a setup token sets force nak, which clears this bit. ep0 count : contains counts of bytes in the endpoint buffers. ep1/2 count : contains counts of bytes in the endpoint buffers. definition of this register depends on the ep mode as illustrated in table 12: ep out count : set by the sie to indicate the number of bytes received in the most recent out transaction. invalid while out serviced is set. ep in count : set by firmware to indicate the number of bytes to transfer in the next in transaction. invalid while in packet ready is set. t ab le 12. ep 1/2 counts ep mode description ep1/2 count 000 ep1 off , ep2 off gp r 001 ep1 in ep2 off gpr ep1 in count 3:0 010 ep1 out , ep2 off gpr ep1 out count 3:0 011 ep1 contr ol ep1 out count 3:0 ep1 in count 3:0 100 ep1 out , ep2 out ep2 out count 3:0 ep1 out count 3:0 101 ep1 in, ep 1 o ut ep 1 o ut count 3:0 ep1 in count 3:0 110 ep1 out , ep 1 i n ep 1 i n count 3:0 ep1 out count 3:0 111 ep1 in ep2 in ep2 in count 3:0 ep1 in count 3:0
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 27 1 figure 16. comm register s (non-usb modes: b0?f) addr b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf name d7 d6 d5 d4 d3 d2 d1 d0 port a port b sie mode low priority intr mode 3:0 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 byte rcv xmit done low priority mask same as low priority intr high priority intr high priority mask over- run error rcv comm error rcv done same as high priority intr comm csr rcv ready xmit ready p acket size rcv p acket size xmit p acket size byte offsets last byte received offset next send byte offset 1200 baud serial ps/2 usb comm error host abort pb7 intr pb7 msk pb6 intr pb6 msk
z8e520/c520 1.5 mbps usb device controller zilog 28 p r e l i m i n a r y ds97key2005 communication register definitions (non-usb modes) the following definitions describe in detail the specific non- usb mode registers as illustrated in figure 16. port a, port b : same as usb mode. port b6 and b7 are i/o in the gpio mode. sie mode : same as usb mode. low priority intr : this register contains the irq flags of a low-priority communications interrupt. read/write. low priority mask : this register contains mask bits for the irq sources specified in the low priority intr register. a set bit indicates that the corresponding interrupt source is unmasked. n xmit comm error : indicates that a communications error occurred while transmitting a byte. valid only when the sie is in ps/2 mode. indicates that the host aborted the transfer. n xmit done : indicates that xmit packet size bytes have been sent since xmit ready was set. high priority intr : this register contains the irq source flags of a low-priority communications interrupt. the isr should check these bits to determine the cause of the interrupt. read/write. high priority mask : this register contains mask bits for the irq sources specified in the high priority intr register. a set bit indicates that the corresponding interrupt source is unmasked. n overrun error : indicates that rcv ready was clear when rcv done was set. n rcv comm error : indicates that a communications error occurred while receiving a byte, resulting in a framing or parity error. in ps/2 mode, it may also indicate that the host aborted its own transmission. n rcv done : indicates that rcv packet size bytes have been received since rcv ready was set. comm csr : controls the sie in ps/2 and rs232-c mode. n xmit ready : indicates to the sie that the xmit buffer is valid. cleared by sie when xmit done is set. cannot be cleared by firmware. read/write. n rcv ready : indicates to the sie that the most recent packet received has been handled. cleared by the sie after rcv done is set. cannot be cleared by firmware. read/write. n rcv packet size : number of bytes to receive before byte received interrupt. value may not exceed the size specified in rcv buffer size. a ??indicates that the packet size = the buffer size. read/write. n xmit packet size : the number of bytes to send before the xmit done interrupt. a ??indicates that the packet size = the buffer size n last byte received offset : indicates the offset in the receive buffer of the most recent byte received. read only. n next send byte offset : indicates the offset in the xmit buffer of the next byte to be sent. if the host has aborted a ps/2 transmission, it is the offset of the byte that was aborted. read only.
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 29 1 initial states: comm registers, upon changing modes: initial states: port configuration registers: all registers in this state are cleared to 0 on por. addr name d7 d6 d5 d4 d3 d2 d1 d0 0 por t a cleared b y por,or not changed 1 por t b same as p or t a 2 3 4 5 sie 6 contr ol all 0 7 regs 8 9 a b c d e uninit ializ ed f
z8e520/c520 1.5 mbps usb device controller zilog 30 p r e l i m i n a r y ds97key2005 port configuration registers figure 17. p or t con guration register s ( d0?f) addr d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df name d7 d6 d5 d4 d3 d2 d1 d0 port a config 01 port a config 23 port a config 45 port a config 67 port b config 01 port b config 23 port b config 45 port b config 67 port a sink 45 port a sink 67 port b 0 port b 1 port b 2 port b 3 port b 4 port b 5 w ake push/ pull pull dwn on output w ake push/ pull pull dwn on output w ake push/ pull pullup on output w ake push/ pull pullup on output w ake push/ pull pullup on output w ake push/ pull pullup on output w ake push/ pull pullup on output w ake push/ pull pullup on output push/ pull pullup on output comp enable vref 5:4 w ake push/ pull pull dwn on output w ake push/ pull pullup on output w ake push/ pull pullup on output w ake push/ pull pullup on output w ake push/ pull pullup on output w ake push/ pull pullup on output push/ pull pullup on output divider 2:0 a0 a2 a4 a6 b0 b2 b4 b6 a1 a3 a5 a7 b1 b3 b5 b7 comp enable vref 5:4 divider 2:0 comp enable comp enable comp enable vref 5:4 vref 5:4 vref 5:4 divider 2:0 divider 2:0 divider 2:0 comp enable vref 5:4 divider 2 :0 a5 sink 3:0 sink 3:0 sink 3:0 sink 3:0 a4 a7 a6 b0 b1 b2 b3 b4 b5
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 31 1 port register definitions the following definitions describe in detail the specific port registers as illustrated in figure 17. wake : when set, this pin is capable of waking the device on any edge. push/pull : when set, this pin is a push-pull output. when clear, this pin is an open-drain output. ignored if output is clear. pullup on : when set, the pull-up resistor is on. output : when set, the pin? output drivers are enabled. however, the pin may be read at any time regardless of the configuration. sink : indicates the level of current drawn by the current sink on the pin. when sink 1 0, the n-channel output tran- sistor is disabled. when sink = 0, the sink is off and the n- channel output transistor may be enabled according to the output bit. divider : selects one of the three voltage dividers to be placed on the pin. divider 0 indicates no divider. vref : indicates the voltage reference level for the com- parator. ignored if comp enabled is clear. comp enable : when set, the comparator is powered. when clear, the comparator and vref circuitry are pow- ered down. functional descriptions counter/timers . for the z8e20, 8-bit timers t0 and t1 are available to function as a pair of independent 8-bit standard timers, or they can be cascaded to function as a 16-bit pwm timer. in addition, 8-bit timers t2 and t3 are provided but they can only operate in cascade to function as a 16-bit standard timer (figure 18). each 8-bit timer is provided a pair of registers, which are both readable and writable. one of the registers is defined to contain the auto-initialization value for the timer, while the second register contains the current value for the timer. when a timer is enabled, the timer will decrement whatev- er value is currently held in its count register, and will then continue decrementing until it reaches 0, at which time an interrupt will be generated and the contents of the auto-ini- tialization register are optionally copied into the count val- ue register. if auto-initialization is not enabled, the timer will stop counting upon reaching 0 and control logic will clear the appropriate control register bit to disable the tim- er. this occurrence is referred to as ?ingle-shot?opera- tion. if auto-initialization is enabled, the timer will continue counting from the initialization value. software should not attempt to use registers that are defined as having timer functionality. software is allowed to write to any register at any time, but it is not recommended that timer registers be updated while the timer is enabled. if software updates the count value while the timer is in operation, the timer will continue counting based upon the software-updated value. this oc- currence can produce strange behavior if the software up- date occurred at exactly the point that the timer was reach- ing 0 to trigger an interrupt and/or reload. similarly, if software updates the initialization value regis- ter while the timer is active, the next time that the timer reaches 0, it will be initialized using the updated value. again, strange behavior could result if the initialization val- ue register is being written while the timer is in the process of being initialized. whether initialization is done with the new or old value is a function of the exact timing of the write operation. in all cases, the z8e520 will prioritize the software write above that of a decremented writeback. however, when hardware clears a control register bit for a timer that is configured for single-shot operation; the clear- ing of the control bit will override a software write. reading either register can be done at any time, and will have no effect on the functionality of the timer. if a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach 0 before an interrupt is generated. in this case, a single interrupt will be generat- ed, and the interrupt will correspond to the even 8-bit time. for example, timers t2 and t3 are cascaded to form a sin- gle 16-bit timer, so the interrupt for the combined timer will be defined to be that of timer t2 rather than t3. when a timer pair is specified to act as a single 16-bit timer, the even timer registers in the pair (timer t0 or t2) will be de- fined to hold the timer? least significant byte; while the odd timer in the pair will hold the timer? most significant byte. in parallel with the posting of the interrupt request, the in- terrupting timer? count value will be initialized by copying the contents of the auto-initialization value register to the count value register. note: any time that a timer pair is defined to act as a single 16-bit timer, that the auto-reload function will be performed automatically. all 16-bit timers will continue counting while their interrupt requests are active, and will operate in a free-running manner. if interrupts are disabled for a long period of time, it is pos- sible for the timer to decrement to 0 again before its initial interrupt has been responded to. this occurrence is a de- generate case, and hardware is not required to detect this
z8e520/c520 1.5 mbps usb device controller zilog 32 p r e l i m i n a r y ds97key2005 functional descriptions (continued) condition. when the timer control register is written, all tim- ers that are enabled by the write will begin counting using the value that is held in their count register. an auto-initial- ization is not performed. all timers can receive an internal clock source only, so synchronization of timer updates is not an issue. each standard timer that is enabled will be updated every 8th xtal clock cycle. if t0 and t1 are defined to work independently, then each will work as an 8-bit timer with a single auto-initialization register; t0arlo for t0, and t1arlo for t1. each timer will assert its predefined interrupt when it times out, and will optionally perform the auto-initialization function. if t0 and t1 are cascaded to form a single 16-bit timer, then the single 16-bit timer will be capable of performing as a pulse- width modulator (pwm). this timer is referred to as t01 to distinguish it as having special functionality that is not available when t0 and t1 act independently. when t01 is enabled, it can use a pair of 16-bit auto-initial- ization registers. in this mode, one 16-bit auto-initialization value is composed of the concatenation of t1arlo and t0arlo, and the second auto-initialization value is com- posed of the concatenation of t1arhi and t0arhi. when t01 times out, it will alternately initialize its count value us- ing the lo auto-init pair followed by the hi auto-init pair. this functionality corresponds to a pwm where the t1 in- terrupt will define the end of the high section of the wave- form, and the t0 interrupt will mark the end of the low por- tion of the pwm waveform. to use the cascaded timers as a pwm, one must initialize the t0/t1 count registers to work in conjunction with the port pin. the user should initialize the t0 and t1 count reg- isters to the pwm hi auto-init value to obtain the required pwm behavior. the pwm is arbitrarily defined to use the low auto-reload registers first, implying that it had just timed out after beginning in the high portion of the pwm waveform. as such, the pwm is defined to assert the t1 interrupt after the first timeout interval. after the auto-initialization has been completed, decre- menting occurs for the number of counts defined by the auto-init_lo registers. when decrementing again reaches 0, the t0 interrupt is asserted; and auto-init using the auto- init_hi registers occurs. decrementing occurs for the num- ber of counts defined by the auto-init_hi registers until reaching 0, at which time the the t1 interrupt is asserted, and the cycle begins again. the internal timers can be used to trigger external events by toggling port output when generating an interrupt. this functionality can only be achieved in conjunction with the port unit defining the appropriate pin as an output signal with the timer output special function enabled. in this mode, the appropriate port output will be toggled when the timer count reaches 0, and will continue toggling each time that the timer times out. figure 18. z8e520 timer s bloc k dia gram xt al ? 8 t0arhi register data bus t1arhi t0 t1 t1arlo t0arlo pwm p a1 ? 8 xt al = bidirectional ouf ouf irq0 load load irq1 t reg c0? reg c0 1
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 33 1 watch-dog timer. the wdt can be programmed at any- time in the program operation. default value (reset) = 98 ms the rc oscillator is under firmware control. if the oscillator is enabled during usb suspend/chip stop mode, the de- vice will be periodically woke up by the wdt timeout. if the application does not require ?otion detect,?the current that drives the internal oscillator/wdt can be saved. wdt control registers. select time-out values for the wdt are programmable ? to +100%. interrupts. the z8e520 has six different interrupts. these interrupts are maskable and prioritized (figure 19 ). the six sources are divided as follows: . when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the interrupt priority register. all interrupts are vectored through locations in the program memory. when an interrupt machine cycle is activated an interrupt request is granted. all of the subsequent interrupts are thus dis- abled, saving the program counter and status flags, and branching to the program memory vector location reserved for that interrupt. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. emi. lower emi on the z8e520 is achieved through circuit modifications. the z8e520 also accepts external clock from xtal in pin (figure 20). power-on-reset (por) . a timer circuit is triggered by the system oscillator and is used for the power-on reset (por) timer function. the por time allows v cc and the os- cillator circuit to stabilize before instruction execution be- gins. por period is defined as: the por timer circuit is a one-shot timer triggered by pow- er fail to power ok status. the por time is a nominal 100 ms at 6 mhz. the por time is bypassed after stop-mode recovery. halt. halt turns off the internal cpu clock, but not the oscillator. the counter/timer and external interrupts irq0? remain active. the z8e520 recovers by interrupts, either externally or internally. usb reset. detection by the sie of a reset from the host will cause the chip to reset. the reset will be remembered so that the program can decide the source of the reset. the usb reset will act even if the chip is in the stop mode. priority irq 0 tco 1 tc1 2 tc2 3 comm high 4 comm lo w 5 p or t figure 19. interrupt bloc k dia gram i r q i m r 6 6 irq0?rq4 vector select interrupt request global interrupt enable figure 20. oscillator con guration por (ms) = 98 ms xt al1 (in) xt al2 (out)
z8e520/c520 1.5 mbps usb device controller zilog 34 p r e l i m i n a r y ds97key2005 functional descriptions (continued) v bo circuit. the voltage brown out circuit will detect when voltage has dropped below the normal operating voltage. the chip will maintain full core functionality and ram values will be preserved during the range from v min (v cc = 4v) to v bo ; however, it may not meet worst case ac and dc limits. at v bo , the chip will be placed in reset and maintained in that state until v cc exceeds v bo . when this condition is reached, the chip will resume operation. v bo is set by design to 2.7 v 0.2 v. stop. this instruction turns off the internal clock and ex- ternal ceramic resonator oscillation. it reduces the standby current to less than 60 m a. the stop mode is terminated by an interrupt. an interrupt from any of the active (en- abled) interrupts will remove the chip from the stop mode (ports 31?3 including the usb reset. note: the timer cannot generate an interrupt in stop mode because the clock is stopped. the interrupt causes the processor to restart the applica- tion program at the address or the vector of the interrupt and continue the program at the end of the interrupt ser- vice routine. in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid sus- pending execution in mid-instruction. as a result, the user must execute a nop (opcode=ffh) immediately before the appropriate sleep instruction, such as: ff nop ; clear the pipeline 6f st op ; enter st op mode or ff nop ; clear the pipeline 7f hal t ; enter hal t mode
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 35 1 z8 plus system registers the registers displayed in figures 21?7 represent zilog? new z8 plus architecture. for a complete overview of this new technology, please refer to the z8 plus user? manual (um97z8x0300) available at your local zilog sales office. figure 21. interrupt request register d7 d6 d5 d4 d3 d2 d1 d0 0fa irq irq0 = timer0 timeout irq1 = timer1 timeout irq2 = timer2 timeout ir q3 = high priority comm irq 4 = low priority comm irq5 = port s reserved (must be 0) reserved (must be 0) fixed interrupt priority: irq0 > irq1 > irq2 > irq3 > irq4 > irq5
z8e520/c520 1.5 mbps usb device controller zilog 36 p r e l i m i n a r y ds97key2005 z8 plus system registers (continued) figure 22. interrupt mask register figure 23. stac k p ointer d7 d6 d5 d4 d3 d2 d1 d0 0fb imr reserved (must be 0) 1 = irq bit n enabled 0 = irq bit n masked 1= global interrupts enabled 0 = global interrupts disabled d7 d6 d5 d4 d3 d2 d1 d0 0ff stack pointer next stack addresses
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 37 1 figure 24. tctlhi register d7 d6 d5 d4 d3 d2 d1 d0 0c1 tctlhi reset source 0 = stop mode enabled 1 = stop mode disabled d6 d5 d4 wdt timeout value 0 0 0 disabled 0 0 1 65,536 0 1 0 131,072 0 1 1 262,144 1 0 0 524,288 1 0 1 1,048,576 1 1 0 2,097,152 156 400 1200.0 1 1 1 4,194,304 (rc clocks to timeout?) 1 = rc enabled 0 = rc disabled 5 12 39.3 ms 10 25 78.0 ms 19 50 156.0 ms 38 100 312.0 ms 78 200 624.0 ms counts min nom max 300 800 2400.0 ms units ms sie wdt por ?: rc frequency = 40 khz (range : 20 to 100 khz)
z8e520/c520 1.5 mbps usb device controller zilog 38 p r e l i m i n a r y ds97key2005 z8 plus system registers (continued) figure 25. tctllo register d7 d6 d5 d4 d3 d2 d1 d0 0c0 tctllo timer status d2 d1 d0 t0 t1 0 0 0 disab. disab. 0 0 1 enab. disab. 0 1 0 disab. enab. 0 1 1 enab. enab. 1 0 0 t01 (pwm) 1 0 1 enab.(*) disab. 1 1 0 disab. enab.(*) 1 1 1 t32 (16 bit) (note: (*) indicates auto-reload is active.) 1 = t32 16-bit timer enabled with auto-reload active 0 = t2 and t3 timers disabled d6 1: pwm mode in t0 (pa1 is output) no te: timer t 01 i s a 16-bit pwm timer formed by cascading 8-bit timers t1 (msb) and t0 (lsb). timer t32 is a st and ard 16-bit timer formed b y cascading 8-bit timers t3(msb) and t2(lsb). d3 0: 6 mhz cr n o te: clock ?ivide by mode ( ? ) allo ws for lo wer po wer for rs232 or f aster c pu execution with zie a t normal 6 mhz clock ra te. d3 1: 12 mhz cr d4 0: core clk = ? ( xtal v alue) d4 1: core clk = xtal ? 2 d7 1: capture mode in t0 (pa0 is input)
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 39 1 figure 26. z8e520 register p ointe d7 d6 d5 d4 d3 d2 d1 d0 0fd rp must be 0. (only page0 is implemented on z8e520.) df d0 cf c0 3f 30 2f 20 1f 10 0f 00 the upper nibble of the register file address provided by the register pointer specifies the active working register group. register pointer r15 r0 r15 r0 r15 r0 r15 r0 r15 r0 r15 r0 register group 0 register group 1 register group 2 * (active) register group 3 register group c register group d the lower nibble of the register file address provided by the instruction points to the specific register. * register group 2 is active if rp = 20h.
z8e520/c520 1.5 mbps usb device controller zilog 40 p r e l i m i n a r y ds97key2005 z8 plus system registers (continued) figure 27. fla gs register d7 d6 d5 d4 d3 d2 d1 d0 0fc flags stop mode recovery flag (smr) wdt reset flag (wdt) half-carry flag (hc) decimal adjust flag (da) overflow flag (ovf) sign flag (s) zero flag (z) carry flag (c)
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 41 1 package information figure 28. 20-pin dip p ac ka g e figure 29. 20-pin soic p ac ka g e
z8e520/c520 1.5 mbps usb device controller zilog 42 p r e l i m i n a r y ds97key2005 ordering information for fast results, contact your zilog sales office for assistance in ordering the part required. codes package p = plastic dip v = plastic leaded chip carrier f = quad flat pack speed 06 = 6 mhz environment c = plastic standard temperature s = 0 c to +70 c 6 mhz 6 mhz 20-pin dip 20-pin soic z8e520psc z8e520ssc Z8C520PSC z8c520ssc example: z 8e520 06 p s c envir onmental flow t emperatur e package speed pr oduct number zilog pr efix is a z8e520, 6 mhz, soic , 0 c to +70 c, plastic standar d flow
z8e520/c520 zilog 1.5 mbps usb device controller ds97key2005 p r e l i m i n a r y 43 1 development projects: customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems and delays. no production release is authorized or committed until the customer and zilog have agreed upon a customer procurement specification for this product. pre-characterization product: the product represented by this cps is newly introduced and zilog has not completed the full characterization of the product. the cps states what zilog knows about this product at this time, but additional features or nonconformance with some aspects of the cps may be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery may be uncertain at times, due to start-up yield issues. low margin: customer is advised that this product does not meet zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on zilog liability stated on the front and back of the acknowledgment, zilog makes no claim as to quality and reliability under the cps. the product remains subject to standard warranty for replacement due to defects in materials and workmanship. ?1998 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax 408 370-8056 internet: http://www.zilog.com

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